Electrically erasable programmable read-only memory (EEPROM) has been widely used as the storage device in integrated circuits. There are various types of EEPROMs and corresponding memory cells. FIG. 1 illustrates a portion of a conventional EEPROM array 100, which includes a plurality of memory cells arranged in rows and columns. Word-lines (denoted as CG) and assistance gates AG are parallel to each other and form transistors with the underlying diffusion regions (including the denoted drains and sources). The drains of EEPROM cells in a same row are interconnected through metal lines (not shown), while the drains in different rows are disconnected from each other. Sources are interconnected through source-lines, which include diffusion regions extending in the column direction. The source-lines of the entire EEPROM array 100 are interconnected. Each of the memory cells in EEPROM array 100, for example, cell 102, includes two MOS devices, selection device 110 and storage device 112. Accordingly, each of the EEPROM cells occupies a relatively great chip area.
On the other hand, there are other types of EEPROM cells occupying less chip area, for example, the EEPROM cells comprising split gates. Although split-gate EEPROM cells are small, they typically include two polys, with one of the polys being used as a floating gate, and the other being used as a control gate. This type of EEPROM cell also suffers from drawbacks. Due to the extra poly, the manufacturing process is not compatible with the formation processes of logic MOS devices, which are single-poly devices. In addition, high program voltages, for example, about 10 volts, are needed, which require additional high-voltage devices to provide the high voltages.
Accordingly, what is needed in the art are EEPROM cells and the respective arrays that may be formed using logic-compatible processes and can be operated under low operation voltages.